The present invention relates to a semiconductor memory. By way of example, it relates to techniques which are effective when utilized for a multiport memory etc. built in a gate-array integrated circuit etc.
A gate-array integrated circuit has a built-in multiport memory. The multiport memory is employed as, for example, a register file when the gate-array integrated circuit constitutes, for example, a digital processor such as computer.
The multiport memory is described in, for example, "IEEE 1987, Materials for CICC (Custom Integrated Circuits Conference)," pp. 195-198.
In the multiport memory (dual-port memory) having two ports as stated in the above literature, addresses designated by both the ports agree in some cases. When an operating condition arises, on occasion, during which both of the ports are set in a read mode, a read operation at the agreeing address is executed without any change, and the resulting read data is output. In addition, when both the ports are set in a write mode at this time, the write operation of either of the ports is inhibited so as to prevent an unspecified write condition from developing. Further, when one port is set in the write mode and the other port in the read mode, there is adopted a step wherein the read operation of the other port is inhibited or a step wherein the read operation of the other port is carried out at the point of time at which the write operation of one port has ended.
In a case where the multiport memory is employed as the register file of a computer or the like, one port is often used as a read-only port. Herein, in a case where the other port is set in the write mode and where the addresses designated by both the ports are in agreement, there is often adopted the aforementioned latter step wherein the read operation of one port is performed upon the end of the write operation of the other port.
With such a step, however, the wait time involved of the port set in the read mode becomes undesirably lengthened, resulting in a corresponding long access time of the multiport memory. For this reason, the operating speed of the computer or the like including the multiport memory becomes decreased thereby limiting the throughput capability thereof.
An object of the present invention is to provide a multiport memory from which the latest write data can be read at high speed even in a case where addresses designated by at least two ports are in agreement and where one port is set in a write mode, while the other port is set in a read mode. Another object of the present invention is to further enhance the throughput capability of a digital processor including a multiport memory.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.